Modern day non-volatile memory products incorporate the ability to electrically program and erase the memory cells. In most manifestations, the erase operation is preformed on a subset of cells and not individually cell-by-cell, as normally performed during the programming operation. This means that erasure conditions are applied to the subset until the last (slowest) cell finishes erasure, i.e. is verified as passing a predetermined level (erase verify).
Memory products incorporating tunneling enhanced hot hole injection during erasure, as in NROM (nitride read-only memory) technology, require high biasing of the transistor junction to create the injected holes, through band-to-band tunneling, as may be seen in FIG. 1. Charge injection must be controlled to insure proper device operation, and accordingly, step and verify algorithms are typically implemented. In a typical algorithm, charge is injected at a certain bias following by a verify operation to ascertain whether the cell has reached its destination. If the destination has not been achieved, stronger charge injection is initiated via a higher bias and vice versa. For tunneling enhanced hot hole injection, this flow usually has to be performed on both sides of the memory cell separately, resulting in longer erase time and lower performance.
During the lifetime of the device and specifically after intensive cycling (consecutive program and erase operations) the voltages required to erase an NROM or NROM-like cell increase. For example, FIG. 2 illustrates an example of a typical prior art erase curve of an NROM cell before and after cycling. The graph shows the degradation of the erase operation, in which higher voltages are required to erase the cell after cycling.
FIG. 3 illustrates another example of the detrimental effects cycling has on the erasure voltage. Specifically, FIG. 3 illustrates erase voltage and step count of a prior art NROM based memory product, as a function of the number of program/erase operations (cycle count) performed on the device. The drain voltage (Vppd) increases up to a certain voltage (e.g., 7.1 V, the maximum allowed value in the specific product shown in the graph), together with an increase of the number of pulses. After reaching the maximum allowed voltage, the voltage level becomes clamped.
Since the initial erase voltages are set during the beginning of life testing, a time penalty in the erase operation is accumulated, which translates into low product performance in the middle to end of life range.
Many options have been proposed and tried in the prior art to enhance the efficiency of the hole-injection-based erase flow. One option applies an extra erase pulse at a higher level than the last pulse used to reach full erasure for improving reliability. Application of additional pulses is taught in various patent documents, such as U.S. Pat. No. 6,700,818 and US Patent Applications 20050117395 and 20050058005, all assigned to the present assignee of the present application, the disclosures of which are incorporated herein by reference.
Another option uses large voltage strides between consecutive steps. However, this may result in poor control of the operation. Still another option uses multiple strides. Since charge injection is usually performed for many cells in parallel, the rationale of this option is that large strides can be incorporated until a first cell ensemble reaches a target, followed by smaller strides until the full population is done.
Another option is that of a learning phase, in which a prior step level ascertained from a previous cell group or erase operation of the same group is implemented on the rest of the array in order to achieve fast convergence Yet another option calls for dialing in the first pulse level during product sort. However, this does not insure a low pulse count over time.
Another option uses multiple verify levels. This may achieve a faster convergence to the final pulse level, but requires a more intricate design and a longer verify time. Another option calls for alternating between the two sides of the cell in the pulse application/verification operations This approach may result in a twofold improvement in erase performance, but may lead to reduced control.
Another option uses increased erase parallelism through the reduction of the power consumption. In another option, erase verification is stopped if sufficient cells fail erasure. Erase verification then continues after applying an additional erase pulse, at the address of the first failure. However, in all of the abovementioned prior art methods, all cells in the erase group must pass several erase verifications, including a penalty of associated word line switching overhead, before the erase operation is completed.